| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82345
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3086
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0676
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-308
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate |
2019-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ee80ea4c95c103bbcd9b7bd7a57ec247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_98130344b4c1436ade0939d99462b5c3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f72c7833414dbf066ede7ff80e89dea9 |
| publicationDate |
2020-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2020098570-A1 |
| titleOfInvention |
Semiconductor device with multiple threshold voltages |
| abstract |
A method for fabricating a semiconductor device with multiple threshold voltages includes masking a substrate structure to selectively form work-function metal layers on vertical field effect transistors. In the method, a first work function metal layer is formed on a high-k dielectric layer of a substrate structure comprising vertical field effect transistors. The first work function metal layer and the high-k dielectric layer are etched to form gate regions for each vertical field effect transistor. A resist mask is formed over a first of the vertical field effect transistors. The resist mask isolates the first of the vertical field effect transistors from a second of the vertical field effect transistors. A second work function metal layer is selectively formed on the first work function metal layer of the gate region of the second of the vertical field effect transistors. The resist mask is then removed. |
| priorityDate |
2018-09-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |