| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7856
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42384
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42372
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate |
2017-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6bc5c5f45af232f10ee777d2fdc7d16d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_97fdcd07cb106438bda72fc4c4cbdf2c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_888bf566a40c41db8955127fd1def57c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9889130fe059595eec0ab3c8eb270ac4 |
| publicationDate |
2019-03-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2019088755-A1 |
| titleOfInvention |
Vertical transistors having multiple gate thicknesses |
| abstract |
Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure si formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension. |
| priorityDate |
2017-09-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |