http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018308742-A1

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filingDate 2018-01-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_39d3cd30365622b0081dee9e814a118d
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publicationDate 2018-10-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2018308742-A1
titleOfInvention Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap
abstract A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region on a substrate, forming at least two vertical fins on the bottom source/drain region, forming a protective spacer on the at least two vertical fins, forming a sacrificial liner on the protective spacer, forming an isolation channel in the bottom source/drain region and substrate between two of the at least two vertical fins, forming an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel, and forming the dielectric separator on the insulating plug.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11404323-B2
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priorityDate 2017-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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