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filingDate 2018-03-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2018-08-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2018218949-A1
titleOfInvention Multiple gate length vertical field-effect-transistors
abstract Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a first portion of a source contact layer formed on a substrate. At least a second portion of the source contact layer is recessed below the first portion of the source contact layer. The mask layer is removed and a first spacer layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer are formed. First and second trenches are then formed. A first channel layer is epitaxially grown within the first trench. A second channel layer is epitaxially grown within the second trench. A length of the second channel layer is greater than a length of the first channel layer.
priorityDate 2015-12-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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