| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bf83328d853bc7476ca10212837b3a01 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0332
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30625
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11548
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11575 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11548
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11575
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-308
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065 |
| filingDate |
2016-12-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5dc2941c312535e13fe8a497284030fa
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c74afc4aacd07372f5389ef18b142e8e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_822b1f90464260cce12a44ae7fc60634
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5f5d46fd81514278a65874375642599f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a9e23eee244ebe5a28ccd58e1ed1dd63 |
| publicationDate |
2018-07-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018190537-A1 |
| titleOfInvention |
Methods for removal of hard mask |
| abstract |
Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. The substrate includes at least first and second regions. The first region includes a memory region and the second region includes a logic region. A hard mask layer is formed covering the substrate and the isolation regions with non-planar surface topology. The method includes selectively processing an exposed portion of the hard mask layer over a select region while protecting a portion of the hard mask layer over a non-select region. The top substrate area and isolation regions of the non-select region are not exposed during processing of the portion of the hard mask layer over the select region. Hard mask residue is completely removed over the select region during processing of the exposed portion of the hard mask layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111341728-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11037990-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11387150-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11784054-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021082710-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11164874-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11404328-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115084030-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11659706-B2 |
| priorityDate |
2016-12-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |