http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018096177-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-4401 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5389 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5386 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5385 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5384 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06K7-10198 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0246 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-4405 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06K7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-538 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-26 |
| filingDate | 2016-10-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_97910689dc688a41abb5796ccabad3fe http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_348c6507914172e56007a0c4beca3ad6 |
| publicationDate | 2018-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2018096177-A1 |
| titleOfInvention | Systems, methods, and apparatuses for implementing late fusing of processor features using a non-volatile memory |
| abstract | In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing late fusing of processor features using a non-volatile memory. For instance, there is disclosed in accordance with one embodiment a functional semiconductor package, including: a processor core configurable via a plurality of configuration registers; a non-volatile storage, in which a first portion of the non-volatile storage includes permanently lockable storage that once written cannot be overwritten or modified, and in which a second portion of the non-volatile storage includes the plurality of configuration registers; a first write interface to the non-volatile storage, in which the permanently lockable storage of the non-volatile storage is wirelessly writable externally from the functional semiconductor package via the first write interface; a second write interface to the non-volatile storage through which the plurality of configuration registers are writable; configuration data for the processor core written wirelessly into the permanently lockable storage of the non-volatile storage; and in which the configuration data is distributed into the plurality of configuration registers via the second write interface at every boot of the functional semiconductor package. Other related embodiments are disclosed. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2020038604-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018107972-A1 |
| priorityDate | 2016-10-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 72.