| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0292
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14679 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2017-10-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b90232432b1b2a1f0cdb01aa84d55af9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa33aca5b1c25b0a70dedaf4facba75b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b216a1fbec3e4bdacbad393880bc2188 |
| publicationDate |
2018-03-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2018090489-A1 |
| titleOfInvention |
Asymmetrical vertical transistor |
| abstract |
A method of fabricating asymmetric vertical field effect transistors (VFETs) includes forming mandrels above a substrate comprising a first semiconductor material. A first set of spacers is formed adjacent to each side of the mandrels, and trenches are formed in portions of the substrate that are not below one of the mandrels or one of the first set of spacers. The method also includes filling the trenches with a second semiconductor material that is different from the first semiconductor material and forming a second set of spacers adjacent to each respective one of the first set of spacers. The second set of spacers is above the second semiconductor material. A plurality of fins is formed such that each one of the plurality of fins includes a portion of the substrate and a portion of the second semiconductor material. Gates are formed between each adjacent pair of fins. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10833079-B2 |
| priorityDate |
2016-09-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |