| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26513 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B20-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11568
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5256
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-265
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11206
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11575 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-112
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-525 |
| filingDate |
2016-07-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c934eed3b3b797757295c51e01dd1367 |
| publicationDate |
2016-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2016315093-A1 |
| titleOfInvention |
Method of manufacturing a nonvolatile memory cell and a field effect transistor |
| abstract |
To provide a semiconductor device having mix-loaded therein a nonvolatile memory cell and a field effect transistor at a reduced cost. A method of manufacturing a semiconductor device includes pattering a conductor film by using an additional mask that covers a gate electrode formation region of a memory formation region and exposes a main circuit formation region (field effect transistor formation region) and thereby forming a gate electrode of a nonvolatile memory cell in the memory formation region and then forming an n − type semiconductor region of the nonvolatile memory cell in a semiconductor substrate by ion implantation using the above-mentioned additional mask without changing it to another one. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10957704-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11672124-B2 |
| priorityDate |
2014-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |