| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42344
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate |
2020-01-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-03-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f0a9f051847e029ab42e7c3f5cd80109
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_20553ae85326c584502f0dd0f44cd8c0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fd8d43362ded6083a0dddb71ec7d6ea7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_361440fc0a747aafa3db116225a582eb |
| publicationDate |
2021-03-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10957704-B2 |
| titleOfInvention |
High voltage CMOS with co-planar upper gate surfaces for embedded non-volatile memory |
| abstract |
The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size. |
| priorityDate |
2014-07-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |