http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016064777-A1

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e
classificationCPCAdditional http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02E60-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01M10-425
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0692
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41741
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3114
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01M10-42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
filingDate 2015-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c1d40333bf6f5a277324627758fb77ba
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0dbc86ff2f748f7bd3ad374aa1f96196
publicationDate 2016-03-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2016064777-A1
titleOfInvention Semiconductor device and manufacturing method of semiconductor device
abstract A semiconductor device capable of reducing an inter-source electrode resistance RSS(on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019074273-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2023317841-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107591574-A
priorityDate 2012-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

Predicate Subject
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2001045635-A1
isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID28486
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419491870

Total number of triples: 35.