| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2014-08-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b51cd341fdac0f475a1485611db3d661 |
| publicationDate |
2016-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2016049482-A1 |
| titleOfInvention |
Structure and formation method of semiconductor device with gate stack |
| abstract |
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device also includes a contact etch stop layer over the semiconductor substrate and sidewalls of the gate stack. The semiconductor device further includes a dielectric layer over the contact etch stop layer. In addition, the semiconductor device includes an interfacial layer between the contact etch stop layer and the dielectric layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10269621-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111435684-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111244038-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9899321-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10535555-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11121030-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10388770-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-116544180-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10177241-B2 |
| priorityDate |
2014-08-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |