| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bce787970b69aeb08d159e7c101c9ed7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01J37-32091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02068
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2014-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ef8cf4cd33d98fa4ec1254657b946c03
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d04be56a9d142d17374c31321a508079
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3dde0112a885e960a22e6c3d10dc8b59 |
| publicationDate |
2015-12-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2015348902-A1 |
| titleOfInvention |
Protective via cap for improved interconnect performance |
| abstract |
Exemplary methods of forming a semiconductor structure may include etching a via through a semiconductor structure to expose a first circuit layer interconnect metal. The methods may include forming a layer of a material overlying the exposed first circuit layer interconnect metal. The methods may also include forming a barrier layer within the via having minimal coverage along the bottom of the via. The methods may additionally include forming a second circuit layer interconnect metal overlying the layer of material. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10770314-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018350634-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11756828-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102112116-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20180131332-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020106386-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10858727-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I685044-B |
| priorityDate |
2014-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |