| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66628 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7836
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66492
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2013-07-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd631ccf8efca2f8e64eab5fd7fd2491 |
| publicationDate |
2015-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2015008538-A1 |
| titleOfInvention |
Partially recessed channel core transistors in replacement gate flow |
| abstract |
An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion of the transistors. Elevating the LDD regions is accomplished by a selective epitaxial process prior to LDD implant. Recessing the replacement gates is accomplished by etching substrate material after removal of sacrificial gate material and before formation of a replacement gate dielectric layer. Elevating the LDD regions and recessing the replacement gates may increase a channel length of the MOS transistors and thereby desirably increase threshold uniformity of the transistors. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10685967-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106910686-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019279992-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017345719-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10297602-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2017171881-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9953873-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016056261-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11527540-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018337188-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018315832-A1 |
| priorityDate |
2013-07-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |