patent/US-2013143364-A1

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filingDate	2011-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor	http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_683e503e3fafe69aad3df8ba422a2fcc http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bcc0d17975aa059db48fff1090a63540 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_540fe063d6dd145bf4c5dc8f68fa96a0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1166dd5ae9ded06dc87f858d003bf435 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ebce9b8015adc1e0899d7e05c7e62d4b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b5a8f12ee8fa719704034d2db0f71776
publicationDate	2013-06-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber	US-2013143364-A1
titleOfInvention	Method of processing solder bump by vacuum annealing
abstract	A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.
isCitedBy	http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9773726-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11410954-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2018077798-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11470727-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2569466-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2569466-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9515035-B2
priorityDate	2011-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type	http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 84.