| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_83e284cb6a52f1e7b8c843b6ee59d6ff
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_37732d1649208e0b893a54de0f467570
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a5b448dafe1a9e12b08c60d80e2dfeda |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7849
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78603
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1054
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66772
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78687 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-0392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-308 |
| filingDate |
2010-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3f725f07e9a9eda1bed1168031f47f05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_86e3425e1b6913fca87b5490fec56d23 |
| publicationDate |
2012-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2012049280-A1 |
| titleOfInvention |
Strained Semiconductor Using Elastic Edge Relaxation Of A Stressor Combined With Buried Insulating Layer |
| abstract |
An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9299837-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9368344-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014138796-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113035716-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10446548-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016086803-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018212056-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-4060716-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8642430-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9543214-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114823738-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018083006-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9312339-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9799675-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9576798-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9818874-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/FR-3012666-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8975697-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9305828-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9318372-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104659046-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103489779-A |
| priorityDate |
2010-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |