| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36d1d9c59848bff6ad5f55923d1290f5 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-981
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S977-936
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y99-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82345
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42364
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823468
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82385 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-72
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate |
2010-07-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bf4e0daf4f4e4c02f7778f10e523d654
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5c304639e3dcf3fd2549453c5c8e201f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fc611ef3860652e3515bfc6ae0f32e83 |
| publicationDate |
2011-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2011012180-A1 |
| titleOfInvention |
Method of forming a cmos structure having gate insulation films of different thicknesses |
| abstract |
The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8809850-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8432190-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9893204-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8901559-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011254617-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010230734-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9209251-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9508742-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8669605-B2 |
| priorityDate |
1996-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |