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filingDate 2010-03-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bfa85658d963978dd998e2f3df0a5ee7
publicationDate 2010-09-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2010227470-A1
titleOfInvention Manufacturing Method of Semiconductor Integrated Circuit Device
abstract In a formation process of a semi-global interconnect in a Cu damascene multilayer wiring structure, it is the common practice, upon formation of the damascene wiring structure, to remove an etch stop insulating film from a via bottom by dry etching and then carry out nitrogen plasma treatment to reduce carbon deposits on the surface of the via bottom. Study by the present inventors has revealed that when a sequence of successive discharging for the removal of electrostatic charge by using nitrogen plasma and transportation of the wafer is performed, a Cu hollow is generated on the via bottom at the end of the via chain coupled to a pad lead interconnect having a length not less than a threshold value. According to the invention, in a via hole formation step in a damascene semi-global interconnect or the like, dry etching treatment of a via-bottom etch stop film is performed and then, after nitrogen plasma treatment in the same treatment chamber, electrostatic charge removal treatment by using argon plasma is performed.
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