http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010072483-A1

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filingDate 2009-05-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_567bf20845517e2a9d4b57b65b3406df
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publicationDate 2010-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2010072483-A1
titleOfInvention Thin film transistor array panel and method for manufacturing the same
abstract A thin film transistor array panel according to the present invention includes: a gate line formed on a substrate and including a gate electrode; a gate insulating layer formed on the gate electrode; a mold layer formed on the gate insulating layer and having an opening overlapping the gate electrode; a semiconductor layer filled in the opening; a data line formed on the mold layer and including a source electrode contacted with the semiconductor layer; a drain electrode contacted with the semiconductor layer on the mold layer and facing the source electrode; a passivation layer formed on the data line and the drain electrode; and a pixel electrode formed on the passivation layer and connected to the drain electrode, wherein the passivation layer, the source electrode, and the drain electrode have at least one through-hole connected to the opening.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011037074-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110673414-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019011831-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8405088-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9269796-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2014121469-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11187950-B2
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Total number of triples: 33.