http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009130807-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-0385 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-0383 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 |
| filingDate | 2009-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9230bb18d444000459f0b3c9bff0567a |
| publicationDate | 2009-05-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2009130807-A1 |
| titleOfInvention | Trench DRAM Cell with Vertical Device and Buried Word Lines |
| abstract | A DRAM array having trench capacitor cells of potentially 4F 2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7883962-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010297819-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10515801-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7785961-B2 |
| priorityDate | 1998-12-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 38.