| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-10734
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0557
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-09854
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05009
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-3436
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05001
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13012 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-112
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-488 |
| filingDate |
2007-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0cd381fa77919098ff0e1a380fa61d41 |
| publicationDate |
2008-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2008265428-A1 |
| titleOfInvention |
Via and solder ball shapes to maximize chip or silicon carrier strength relative to thermal or bending load zero point |
| abstract |
A method of modifying via and solder ball shapes for maximizing semiconductor chip or silicon carrier strengths relative to thermal expansion and bending load zero points. The method entails modifying circular annular vias into elliptical annular vias so as to reduce stress concentration factors in the chip or carrier at the vias and solder balls. The reduction in the stress concentration is effected in the semiconductor chip or silicon carrier in regions proximate the vias and in wiring layers at the ends of the vias. |
| priorityDate |
2007-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |