http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007257318-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_97596f7a6b895805fd4b36669d720439 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_eef3f33abd457b39b6c9efa0c1e10eaa |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823468 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823864 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-94 |
| filingDate | 2006-05-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2af762d7c23080ffca33218551c2c2df http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f8d1d103d8cb5abac426ed035e9b3f7b |
| publicationDate | 2007-11-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2007257318-A1 |
| titleOfInvention | Method of Manufacturing Semiconductor Integrated Circuit Device, and Semiconductor Integrated Circuit Device Manufactured by the Method |
| abstract | Provided are a more stable semiconductor integrated circuit device and a method of manufacturing the same. The method includes providing a semiconductor substrate comprising a first transistor region having a stacked structure of a first gate insulating layer and a first gate and a second transistor region having a stacked structure of a second gate insulating layer and a second gate, forming a blocking layer in the first transistor region, conformally forming a second oxide layer on lateral surfaces of the second gate insulating layer and the second gate and on an exposed surface of the semiconductor substrate by performing oxidation in the second transistor region, removing the blocking layer of the first transistor region, forming a pre-spacer layer on the entire surface of the semiconductor substrate, forming a first spacer by anisotropically etching the pre-spacer layer of the first transistor region and forming a second spacer by anisotropically etching the second oxide layer and the pre-spacer layer of the second transistor region, and forming source/drain regions in the semiconductor substrate to complete a first transistor and a second transistor. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111599667-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2013164940-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8664125-B2 |
| priorityDate | 2006-05-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.