| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_17e6412a4d5ccbe9d0947ac93e162b2c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_72c6ec5d86ce14c4d82ef0ab843647d7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8869a61ba57326b487e210f28271f02a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7815
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1087 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66704
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82345
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0248 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-94 |
| filingDate |
2006-12-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1aa1f1e11da5e5a39ad85c52cd6ccd60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52dff7ea82949ef65cbffbed718d21cf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e23d037280a10bb2ea0bcd262c832992 |
| publicationDate |
2007-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2007138566-A1 |
| titleOfInvention |
Semiconductor device and manufacturing method of the same |
| abstract |
A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed to be P-type. The protection circuit includes a planar gate horizontal type offset P-channel MOSFET and the conduction type of the gate electrode is assumed to be N-type. These gate electrode and gate electrode are formed in separate steps. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9825147-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8835254-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011215399-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016351690-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014110777-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112768356-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102157414-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9525037-B2 |
| priorityDate |
2005-12-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |