| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-09701
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3043
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-492
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-78 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-304
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-301
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L47-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-492
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-329 |
| filingDate |
2001-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3ee39b18411e3e1279e31aca81c0373c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_549348decfb3ad91217f6a1ee997fdc0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7be2a81633df394c6a5e9806e2fc9801 |
| publicationDate |
2004-05-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2004087145-A1 |
| titleOfInvention |
Semiconductor device and method of manufacturing |
| abstract |
A method of manufacturing a semiconductor device includes the steps of: taking a semiconductor wafer ( 8 ); defining non-conductive region ( 11 ) and a conductive region ( 15 ) providing electrical contact means ( 10 ) at the conductive region; and separating the wafer into a plurality of dies. By using wafer scale fabrication, thousands of devices may be packaged simultaneously in single process steps without significant operator intervention compared to the conventional packaging processes. An insulating wafer ( 12 ) may be located over the semiconductor wafer and bonded thereto, the insulating wafer having a plurality of tapered apertures ( 13 ) therethrough which are aligned with conducting regions of the semiconductor wafer. |
| priorityDate |
2000-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |