| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9fc0a00eab3a757e8324b1e887d7ba97 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02381
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02521
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02505
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02488 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N30-079
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B29-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B29-406
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B29-403
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B25-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N30-074
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N30-10516
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B29-48 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-20 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C30B25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C30B25-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L41-22 |
| filingDate |
2001-07-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e2fafd9cf90fcfb0bdde8c76bdc4a8e5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1d801ec1b86ce839e687cbc9894ca18b |
| publicationDate |
2003-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2003010974-A1 |
| titleOfInvention |
Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials |
| abstract |
High quality epitaxial layers of piezoelectric monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the piezoelectric monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying piezoelectric monocrystalline material layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2019244174-A3
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014051400-A |
| priorityDate |
2001-07-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |