http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2002123243-A1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76801 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3146 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31629 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02131 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-022 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02211 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-314 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2002-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bfb5471d95eac867c21a8307b73678c3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b141b5ab45165e7474ec8a360ea744d8 |
| publicationDate | 2002-09-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-2002123243-A1 |
| titleOfInvention | Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning |
| abstract | A composite layer of low k silicon oxide dielectric material is formed on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon. The composite layer of low k silicon oxide dielectric material exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines, deposition rates in other regions comparable to standard k silicon oxide, and reduced via poisoning characteristics. The composite layer of low k silicon oxide dielectric material is formed by depositing, in high aspect ratio regions between closely spaced apart metal lines, a first layer of low k silicon oxide dielectric material exhibiting void-free deposition properties until the resulting deposition of low k silicon oxide dielectric material reaches the level of the top of the metal lines on the oxide layer. A second layer of low k silicon oxide dielectric material, having a faster deposition rate than the first layer, is then deposited over the first layer up to the desired overall thickness of the low k silicon oxide dielectric layer. In a preferred embodiment, the steps to form the resulting composite layer of low k silicon oxide dielectric material are all carried out in a single vacuum processing apparatus without removal of the substrate from the vacuum apparatus. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006038293-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006246719-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-10249649-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006265868-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2004033371-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2002136910-A1 |
| priorityDate | 1999-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 40.