Predicate |
Object |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7832 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823425 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-335 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
filingDate |
2001-09-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5003c4efec5261f8243120b7348aa76d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d67e7de2835a3f04c1b293f82a16ac25 |
publicationDate |
2002-03-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-2002037639-A1 |
titleOfInvention |
Method for farbricating field-effect transistors in integrated semiconductor circuits and integrated semiconductor circuit fabricated with a field-effect transistor of this type |
abstract |
A method for fabricating a field-effect transistor situated within an integrated semiconductor circuit. At least two gate regions each extending between a source region and a drain region and are disposed such that they lie one above the other in a thickness direction of a substrate, thereby reducing the space requirement of the hitherto customary larger field-effect transistors in integrated semiconductor circuits. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8421810-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010046833-A1 |
priorityDate |
2000-09-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |