http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11508757-B2

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filingDate 2021-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2022-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d7ec2393bfb9e5968b05ba5659353ce7
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publicationDate 2022-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-11508757-B2
titleOfInvention Breakdown voltage capability of high voltage device
abstract Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.
priorityDate 2021-01-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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