| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41766 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate |
2020-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-08-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4b976e7a32cb8f4834459b07125677ab
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b29393e6a2c2e1635bb1d23bf8b922c7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bf8ea7675fede279fd95fa82078f324c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_474f2fadb41a048b022bed250a888aa0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a1606c1a986f6240d393262fc18c5a6d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aee150b79fbb85586a8c2c6addcaa8c7 |
| publicationDate |
2022-08-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11411108-B2 |
| titleOfInvention |
Semiconductor device and manufacturing method thereof |
| abstract |
A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet. |
| priorityDate |
2015-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |