http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11004953-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_31da94917d1067c89f7e22444c88a836 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28202 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66484 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28185 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66787 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate | 2019-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-05-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bf0ec60058882f6107e3e14ab38c9f9d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c01373291fc3210fe6e96d803fb4f1de http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6a48532b201b3248db524bac7c685bf1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d2515e3a577c70464806f2dd68515233 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f730c4b364cb1f7eb77b090356abe419 |
| publicationDate | 2021-05-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-11004953-B2 |
| titleOfInvention | Mask-free methods of forming structures in a semiconductor device |
| abstract | A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening. A second material layer is formed over the first material layer on the exposed upper portions of the first material layer in the second opening. An intermix layer is formed in the second opening using the first and second material layers. The protective layer from the second opening is removed to expose the first material layer. |
| priorityDate | 2019-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 47.