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filingDate 2019-03-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2020-11-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb
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publicationDate 2020-11-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-10833191-B2
titleOfInvention Integrating nanosheet transistors, on-chip embedded memory, and extended-gate transistors on the same substrate
abstract Embodiments of the invention are directed to methods of fabricating devices on a substrate. A non-limiting example of the method includes performing memory fabrication operations to form a non-volatile memory device in a first region of the substrate, wherein the memory fabrication operations include forming a first region of a nanosheet stack over the first region of the substrate. The first region of the nanosheet stack includes nanosheet layers of a first type of semiconductor material alternating with nanosheet layers of a second type of semiconductor material. A first portion of the first region of the nanosheet stack is replaced with a control gate of the non-volatile memory device, and a charge trapping region of the non-volatile memory device is provided under the control gate.
priorityDate 2019-03-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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