| abstract |
A method is presented for integrating a first nanosheet transistor and a second nanosheet transistor on a chip. The method includes forming a first stack of alternating layers for the first gate dielectric nanosheet transistor and a second stack of alternating layers for the second gate dielectric nanosheet transistor, removing a first set of sacrificial layers of the first stack of alternating layers of the first gate dielectric nanosheet transistor and removing a first set of sacrificial layers of the second stack of alternating layers of the second gate dielectric nanosheet transistor, and removing a second set of sacrificial layers of the first stack of alternating layers. The method further includes annealing a second set of sacrificial layers to subsequently remove the second set of sacrificial layers of the second stack of alternating layers, and forming a first gate dielectric nanosheet transistor and a second gate dielectric nanosheet transistor. |