| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823468
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4983
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4232
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28123 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2018-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f305f9a082ca36227e516ae901353bdc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_07274a6b9e958a5d48deeb45152ae5b6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_af9b0ed5c62cb9c10030aa1e961f620f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8f77167737b0b1b261a980782426c5f0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_efdfe150d51fb48b73bf965f96c3eae1 |
| publicationDate |
2020-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10811516-B2 |
| titleOfInvention |
Structure and formation method of semiconductor device structure with gate stack |
| abstract |
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021376125-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021036128-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11631748-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11658229-B2 |
| priorityDate |
2014-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |