Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6af9a57049d2d91c036d4f5ab49154cb |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
filingDate |
2018-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2020-09-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_461ad7ffa039b59e0a0db8439512590b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b0c1736f581429f74e2dae6c9a2c78b7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0815d8783594195975782efe7df363c9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8bb0e7f92d1794dd8c4031583e6add1e |
publicationDate |
2020-09-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-10777465-B2 |
titleOfInvention |
Integration of vertical-transport transistors and planar transistors |
abstract |
Structures including a vertical-transport field-effect transistor and a planar field-effect transistor, and methods of forming such structures. First and second sacrificial fins are respectively formed over first and second areas of the first device region. One or more semiconductor fins of the vertical-transport field-effect transistor are formed over the second device region. A first gate electrode of the planar field-effect transistor, which is arranged on the first device region between the first sacrificial fin and the second sacrificial fin, and a second gate electrode of the vertical-transport field-effect transistor, which is wrapped about the one or more semiconductor fins, are currently formed. |
priorityDate |
2018-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |