| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4991
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-165 |
| filingDate |
2016-11-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7819d634f5333494ec9ef45da50a6c44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_86aa5a4933c18c0c272002bfd9bdb94f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ae4da9915cb6f5dd4d057f099fb3f851 |
| publicationDate |
2020-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10741654-B2 |
| titleOfInvention |
Semiconductor device and forming method thereof |
| abstract |
A semiconductor device includes a semiconductor substrate, at least one gate stack, a gate spacer and a dielectric cap. The gate stack is located on the semiconductor substrate. The gate spacer is located on a sidewall of the gate stack. The gate spacer includes a first dielectric layer and a second dielectric layer with different etch properties. The dielectric cap at least caps the gate spacer. The dielectric cap and the second dielectric layer define a gap therebetween. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10930765-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11145540-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11177383-B2 |
| priorityDate |
2016-11-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |