| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02107
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-321
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0276
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0332
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76808
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31138 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-027
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2018-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e7f61dac0b82b38a45582a199404bbc7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cddf25a8e58f6a7bfecf3af41c6bfa8a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_35a171611f2a9a9ba09b92ba04f6ee3c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_710d38b84a1938d74607ac3fe15ba2d0 |
| publicationDate |
2020-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10692755-B2 |
| titleOfInvention |
Selective deposition of dielectrics on ultra-low k dielectrics |
| abstract |
A method for fabricating a semiconductor device includes forming a via in a first dielectric layer arranged on a metal layer. The via exposes a portion of the metal layer. The method includes forming a trench in the first dielectric layer. The method further includes depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the via and the trench and is selectively deposited onto the first dielectric layer. |
| priorityDate |
2018-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |