Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0228 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0228 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-033 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
filingDate |
2018-08-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2020-05-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_98130344b4c1436ade0939d99462b5c3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_710d38b84a1938d74607ac3fe15ba2d0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f72c7833414dbf066ede7ff80e89dea9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9889130fe059595eec0ab3c8eb270ac4 |
publicationDate |
2020-05-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-10665715-B2 |
titleOfInvention |
Controlling gate length of vertical transistors |
abstract |
A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer. |
priorityDate |
2018-08-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |