| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-70
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-373
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-377
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8239
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10832
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1156 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8239
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1156
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 |
| filingDate |
2015-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-01-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_896132a9b7bc95fc32fbb59ca9848661 |
| publicationDate |
2019-01-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10170630-B2 |
| titleOfInvention |
Manufacturing method of semiconductor memory device |
| abstract |
To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied. To provide a semiconductor memory device which has a large number of write cycles. The degree of integration of a memory cell array is increased by forming a memory cell including two transistors and one capacitor which are arranged three-dimensionally. The electric charge accumulated in the capacitor is prevented from being leaking by forming a transistor for controlling the amount of electric charge of the capacitor in the memory cell using a wide-gap semiconductor having a wider band gap than silicon. Accordingly, a semiconductor memory device which can hold stored data even when power is not supplied can be provided. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11296231-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11114449-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11751409-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10388797-B2 |
| priorityDate |
2012-03-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |