http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I713783-B

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filingDate 2017-08-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2020-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-I713783-B
titleOfInvention Self aligned via and method for fabricating the same
abstract A self-aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal.
priorityDate 2016-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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