| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8cf8d77ac0eff1767b22d2fb9445b64d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76849
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-4763 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2007-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d638c8516c97b9c5de78bdedaea97ae3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93a9954e7313c847019241c8566cc39f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d97966e0bd1a2ba27f56da4565bb607a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8805266b989f4efd32e0584087c074af |
| publicationDate |
2008-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-200836259-A |
| titleOfInvention |
Process integration scheme to lower overall dielectric constant in BEoL interconnect structures |
| abstract |
Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9634250-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8735211-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I713783-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I476869-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9142770-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9419219-B2 |
| priorityDate |
2006-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |