| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823864
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66553
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4983 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76 |
| filingDate |
2018-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7ebef6280d5cfbfcc7d42416df8ab8f6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c74b60a20c380a17ad45346a32b6d219
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_856ee882e3900bd18e3f32944fc0f7b9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f638b08d199649c920874fa09e3b9b0c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b51e30378bb17ea6392f81495306b86d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0121ba39763f6be9d0ac3b0b8267b1ec
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fca69ead4d25d3c06ae35a4c685481ae |
| publicationDate |
2020-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I710057-B |
| titleOfInvention |
Semiconductor structure and method for forming the same |
| abstract |
Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions. |
| priorityDate |
2017-11-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |