| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bce787970b69aeb08d159e7c101c9ed7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K2103-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K2101-40 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K26-0006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K26-53
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-268
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K26-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K26-57
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3171
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K26-0624 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065 |
| filingDate |
2014-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d73fddeb26fc0eb13bbd594190fec5ec
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_65d44d073fd68554e33e7243b991d1a7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d2c29980f84a6916bc08c9b3f529827b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34c276a997ef97792881bc568c666e00 |
| publicationDate |
2019-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I647758-B |
| titleOfInvention |
Maskless hybrid laser scribing and plasma etching wafer cutting process |
| abstract |
Describe the maskless hybrid laser scribing and plasma etching wafer dicing process. In one example, a method for cutting a semiconductor wafer having a front surface having a plurality of integrated circuits on the front surface and having a passivation layer disposed between and covering the metal pillar / solder bump pairs of the integrated circuit Metal pillar / solder bump pair, the method involves laser scribe passivation without the use of a masking layer to provide a scribe to expose the semiconductor wafer. The method also involves etching the semiconductor wafer through a scribe line plasma to singulate the integrated circuit, wherein the passivation layer can protect the integrated circuit during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar / solder bump pair of the integrated circuit. |
| priorityDate |
2013-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |