| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823425
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76801
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41783
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-40 |
| filingDate |
2015-05-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f67ef8ccd3f96c624ef8625102a76fdb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dbffbe577124483d0c4cd4aa63d17178 |
| publicationDate |
2018-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I641134-B |
| titleOfInvention |
Semiconductor device and method for manufacturing conductive structure of semiconductor device |
| abstract |
A method of fabricating a conductive structure of a semiconductor device includes the following steps. A plurality of gate structures are formed on the semiconductor structure, and the first dielectric layer is formed in the space between the gate structures. A first process is performed to remove at least a portion of the first dielectric layer in the spaced space. Forming a second dielectric layer covering the gate structure for forming at least one void in the space between the gate structures. A second process is performed to form at least one opening through the second dielectric layer and expose a void located in the space. At least one conductive material is filled into the void exposed by the opening to form a conductive structure between the gate structures. |
| priorityDate |
2015-04-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |