| abstract |
The present disclosure provides a chip package including a semiconductor wafer and a semiconductor die disposed on the semiconductor wafer. The chip package also includes a dielectric layer, which is disposed on the semiconductor wafer and covers the semiconductor die, wherein the dielectric layer is made of a semiconductor oxide material. The chip package further includes a conductive element which penetrates the semiconductor substrate of the semiconductor die and is physically connected to the conductive pad of the semiconductor wafer. |