http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I398943-B

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filingDate 2010-08-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2013-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3ae885aedcf899d77f91620dacf7eae7
publicationDate 2013-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber TW-I398943-B
titleOfInvention Semiconductor package structure and process
abstract A semiconductor package structure including a substrate, a first chip, a second chip, and an interposer is provided. The substrate has a carrying surface and an opposite bottom surface. The first chip disposed on the carrying surface has a first surface and an opposite second surface. The second surface faces the substrate. The first chip has a plurality of through silicon vias (TSVs) and a plurality of first pads and second pads on the first surface. The first pads are electrically connected to the corresponding TSVs. The TSVs are electrically connected to the substrate. The second chip disposed above the first chip exposes a portion of the first surface. The second chip is electrically connected to the corresponding TSVs. The interposer is disposed on the first surface. Top surfaces of the interposer and the second chip are substantially aligned with each other. The interposer is bonded to the second pads.
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priorityDate 2010-08-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 48.