| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2005-09-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2007-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_42d0fab45dffbb7aafd09036ca629611
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6adc57f303730fbc0a5b352b021b13ab
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3df44edac3103949351990b02e857929
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3c21340d3035b56d5b5eedc81336c1d0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_63e239570326879aa8d803aa639f5260 |
| publicationDate |
2007-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I278115-B |
| titleOfInvention |
Semiconductor device and production method thereof |
| abstract |
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region. |
| priorityDate |
2005-06-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |