| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8cf8d77ac0eff1767b22d2fb9445b64d |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76808
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31138
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3213
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302 |
| filingDate |
2002-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2003-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f4fd64f7e0bbc8461637e69111786948
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_76a041ca0a9776e0529844929ae7c59f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed8a136b4b08b70c41cb0b6534411894
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_28447b39d05b6da147c67d928f309f23
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9b6a7b4e1735100bc55aae4adb0df7e8 |
| publicationDate |
2003-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-567554-B |
| titleOfInvention |
All dual damascene oxide etch process steps in one confined plasma chamber |
| abstract |
The present invention reveals a semiconductor dual damascene etching process, which uses a confined plasma etching chamber to integrate all dual damascene steps such as via hole etching, photoresist stripping and barrier layer removal which originally performed in various reactors as a continuous procedure in the confined plasma chamber. The confined plasma chamber including a confinement ring surrounding a wafer and an anti-etching upper electrode plate performs the steps mentioned above under clean mode. The present invention can not only reduce the time period required by the semiconductor dual damascene process but also greatly reduce the manufacturing cost. |
| priorityDate |
2001-08-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |