http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-400545-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c5520dd38cc403678d9f91e0b0ee95fb |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B20-383 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-112 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 1997-12-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2000-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1acfd8c725955be201a1c8cad3f6e8b7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7458d6c65bbb1fb6bbf35aae8b5af217 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9f8b9572fbd0217da47db1f612aa18a9 |
| publicationDate | 2000-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | TW-400545-B |
| titleOfInvention | Semiconductor device and fabrication method therefor |
| abstract | A semiconductor device fabrication method is provided which comprises the steps of: (i) forming a plurality of high concentration diffusion layers of a second conductivity in a semiconductor substrate; (ii) forming a plurality of first gate electrodes extending perpendicularly to the high concentration diffusion layers of the second conductivity on the semiconductor substrate with a first gate insulating film interposed therebetween; (iii) implanting ions of a first conductivity into surface portions of the semiconductor substrate for device isolation by using the first gate electrodes as a mask; (iv) forming side wall spacers on side walls of the first gate electrodes; (v-i) implanting ions of the second conductivity into surface portions of the semiconductor substrate for formation of channel regions by using the first gate electrodes and the side wall spacers as a mask; (vi-i) forming a plurality of second gate electrodes on the ion-implanted channel regions between the first gate electrodes; and (vii) implanting ions of the first conductivity again into surface portions of the semiconductor substrate by using the first gate electrodes and the second gate electrodes as a mask for device isolation. |
| priorityDate | 1997-02-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID458431896 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID24857 http://rdf.ncbi.nlm.nih.gov/pubchem/protein/ACCQ9VCX1 |
Total number of triples: 20.