| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-12105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-81192
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5382
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16237
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16235
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-62
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5223
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5256
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-17 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-31 |
| filingDate |
2019-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_05fa3748fe2396688ab330694a7831ce
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93e658fdd9a9cc9ecb6babb25012da30 |
| publicationDate |
2020-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-202025411-A |
| titleOfInvention |
Interposer circuit,cowos circuit,and method of using interposer circuit |
| abstract |
An interposer circuit includes a substrate and a dielectric layer that is disposed on top of the substrate. The interposer circuit includes two or more connection layers including a first connection layer and a second connection layer that are disposed at different depths in the dielectric layer. The interposer circuit includes a fuse that is disposed in the first connection layer. The first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node. The interposer circuit further includes a first capacitor that is in series with the fuse and is connected between the first and the second connection layers. The interposer circuit also includes first, second, and third micro-bumps on top of the dielectric layer such that the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps. |
| priorityDate |
2018-10-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |