| abstract |
A charge trapping memory element and an article made therefrom are scaled. In one embodiment, the charge trapping memory device includes a substrate having a source region, a drain region, and a channel region electrically connected to the source and the drain. A tunneling dielectric layer is disposed over the channel region of the substrate, and a plurality of charge trapping regions are disposed on the tunneling dielectric layer. The multilayer charge trapping region includes a first deuterated layer disposed on the tunneling dielectric layer, a first nitride layer and a second nitride layer disposed on the first deuterated layer. |