| abstract |
In various aspects of the invention, a wafer package configuration can be provided. The chip package configuration may include: a dielectric layer having at least one die adjacent to the dielectric layer; at least one bonding region on the die, the bonding region being exposed through the dielectric layer; a first material including a first coefficient of thermal expansion, The first material substantially surrounds the die and abuts the dielectric layer; a second material including a second coefficient of thermal expansion substantially surrounding the die and the first material; and electrically connected to the die At least one conductive trace. |